Conventional high speed comparators typically receive a differential input signal at a differential pair of transistors biased by a reference current (e.g., a tail current). In response to the differential input signal, the transistors selectively pass the tail current to one or the other of a pair of diodes. The diode receiving the tail current turns on and the remaining diode turns off. The resulting voltages at the diodes typically feed a gain stage that provides a single ended output signal.
If the differential input signal does not rapidly change, the voltage at the diode in the off state may slowly decay to a very low voltage level well below the threshold voltage of the diode. As a result, if the comparator attempts to switch on the diode (e.g., in response to a change in the differential input signal), the diode voltage may be required to swing from a very low voltage up to its threshold voltage. In contrast, if the differential input signal does rapidly change, the voltage of the diode in the off state may not decay far below its threshold voltage.
The different voltage swings of the diodes associated with different data patterns in the differential input signal may cause conventional comparators to exhibit varying data propagation delays which appear as data dependent jitter (e.g., duty cycle distortion) in the single ended output signal. Such jitter is particularly problematic for high speed comparators. As a result, there is a need for an improved approach to comparator design that reduces data dependent jitter associated with conventional comparators.